Degree Name

Master of Engineering - Research


School of Electrical, Computer and Telecommunications Engineering


The implementation of an accurate face recognition system in a hardware device is very important aspect of various security applications, such as authorisation identification in cash machines and employee attendance using a door access control system. Door access control systems based on face recognition is geared towards simplifying much-difficult face recognition problems in uncontrolled environments. Such systems are able to control illumination; offer neutral pose and improving the sagging performance of many face recognition algorithms. While there have been significant improvements in the algorithms with increasing recognition accuracy, only few research were conducted on implementing these face recognition in hardware devices. Most of the previous studies focused on implementing Principal Component Analysis (PCA) technique in hardware for simplicity with only low recognition accuracy. The aims of this research are: (1) to investigate the existing face recognition systems and their hardware implementations, particularly those who used for developing an embedded door access control system, (2) to select an appropriate face recognition system and develop a MATLAB code for such system and (3) to investigate the feasibility of implementing the developed face recognition system in an FPGA device for a door access control system. Based on current literature it has been proven that, the accuracy of a face recognition system can be extremely improved using a hybrid feature extraction technique. It has also found that the use of K nearest neighbour classification technique based on the City Block metric is simpler and more accurate than other techniques. Consequently in this study, a face recognition system is developed using these techniques. In this system, the facial topographical features are extracted using fixed size input image extraction technique to extract the eyes, nose and mouth facial regions. Gabor filters of 40 different scales and orientations are applied on these three regions to find the Gabor representations. The feature vector of these regions is then determined by computing the maximum intensity of the resulted Gabor representations. In the classification stage, the Nearest Neighbour method (KNN) is used based on City Block distance to calculate the distances between the three regions feature vectors and the corresponding stored vectors. The system results in excellent recognition accuracy using faces94, FEI and ORL databases. It is observed that, high recognition accuracy rate can be obtained when the facial images are taken carefully with front pose and with only slight expression changes.

On the other hand, based on a comparison in an existing literature between different hardware platforms, Field Programmable Gate Array (FPGA) is found to be more efficient in the tasks of the hardware implementation of a face recognition system. FPGA devices have been developed dramatically in a way to allow designers to select various resources and functions to implement many complex designs. FPGA is preferable because of its technical characteristics of parallelism, re-programmability and very high speed, in the implementation of a face recognition system. Therefore, the feasibility of implementing Gabor filter and nearest neighbour face recognition algorithms in a FPGA device is investigated using the Xilinx system generator and ISE project navigator. Distributive arithmetic FIR filter is used to calculate the required convolution operation between the 40 Gabor filters and each input image. The forty Gabor filters are stored as matrices and then loaded to the distributive arithmetic FIR filter using a FDAtool block in the simulation design. The next simulation contains the design of the required function which computes the maximum intensity of each FIR filter output using an M-block from the Xilinx block set. The resulted vector of 40 values represents the feature vector of the input image. The simulation of the City Block distance between this vector and the stored feature vectors is designed and the minimum distance is found using an M-block from Xilinx block set. The resulted minimum distance represents the best match. The simulations design shows the high improvement of the ability of the current FPGA devices and the improvement of the supportive programs which are able to simulate, configure the required design in FPGA devices. This ability can be used to complete the real time door access control system design.

FoR codes (2008)




Unless otherwise indicated, the views expressed in this thesis are those of the author and do not necessarily represent the views of the University of Wollongong.