The occurrence of fault currents and system sensitivity to fault currents are both increasing in modern power systems. Along with extensive damage to network hardware, considerable consumer losses (due to network unavailability) can result from fault current events. One device that is designed to reduce the impact of fault currents and increase network availability is the fault current limiter (FCL). This paper describes the design and development of a 3-phase saturated core high temperature superconducting (HTS) FCL. This particular type of FCL exhibits negligible power losses during the un-faulted state and also provides instantaneous reaction and recovery during fault events. Optimisation of the design parameters for this device is discussed in this paper. Characterisation results from experimental cores and analyses using the finite element method are also discussed in terms of the design process. Finally, the performance of a prototype 3-phase device is experimentally characterised.