A novel microprocessor architecture using only dynamic shift registers as data storage elements

This thesis describes the use of a ring of dynamic shift register stages to implement register storage in a general purpose microprocessor architectural paradigm. The feasibility of such an architecture is shown, and the performance and VLSI space requirements are discussed. The cycling of machine registers through parallel shift registers can be used to distribute data between elements of the processor. This method replaces the traditional internal bus(es) and allows for concurrency of operations. A data identification scheme and control strategy is introduced to allow safe pipelining of instruction sequences that may be interdependent in respect to data produced. The use of simulation to assess performance is discussed, and a brief performance evaluation presented. VLSI implementation costs are compared to those of a bus architecture, taking into account intrinsic overheads associated with controlling each architecture.