Code compression is a field where compression ratios between compiler-generated code and subsequent compressed code are highly dependent on decisions made at compile time. Most optimizations employed by compilers tend to focus on parameters such as program performance, minimizing resource dependencies and sometimes the option of reducing code size. This paper describes a post-compilation technique for the greedy reassignment of general purpose scratch registers to improve Hamming distance based code compression. The code translation renumbers registers based on the frequency of registers used by isomorphic instructions and employs a Gray coding scheme to reduce Hamming distances between similar instructions. Register reassignment has been successfully implemented in areas where the compiler optimizations do not include a particular metric, for example, power savings. Pro-gram values can be reassigned register numbers that reduce overall power consumption of the address bus and register file decoder, at no cost to code size or performance. The application of the register reassignment technique in this paper reduced the number of dictionary vectors required by a program on average by 9.74%. Code compression ratios of register-reassigned binaries were consistently around 3-4% (of original program size) lower than code compression applied to original binaries, with the highest such reduction at nearly 7%. General purpose register reassignment is a technique that allows for gains in compression efficiency with no penalty in hardware. Other techniques that could be trialed include commutative register switching, dead register detection and assignment and complete register re-allocation.
History
Citation
M. Ros & P. Sutton, "A Post-Compilation Register Re-Assignment Technique for Improving Hamming Distance Based Code Compression," in Proceedings of the 2005 International Conference on Compilers, Architecture and Synthesis For Embedded Systems, 2005, pp. 97-104.
Parent title
CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems