In an MMSE based turbo equalization system, a soft mapper calculates the symbol mean and variance based on extrinsic Log-Likelihood-Ratios (LLRs) information coming from a Soft-Input Soft-Output (SISO) decoder. In this paper, we investigate the complexity of this module, and in particular, we employ a 3-segment linear approximation approach to calculate the mean and variance of data symbols from LLRs. For FPGA and VLSI implementation, we propose novel piecewise linear functions which map LLR to the mean and variance directly without the use of any two-variable-input multipliers. Simulation results for 16-QAM and 64-QAM show that the no multiplier approach has close BER performance to the 3-segment linear approximation approach with multipliers. © 2012 IEEE.